If you have no luck to attend this camp, you still can grab a piece of it by attending seminar of Andrew Moore. It will be an open access lecture. Our guest from University of Cambridge will talk about programmable network devices, He will present NetFPGA cards and their world. The biography of presenter can be found in Tutors section.
Date/Time: May 23 2013, 13.30 - 14.30
Location: Room 201, Polanka 3, Faculty of Electronics and Telecomunications Building, Pozań.
Abstract of lecture: The NetFPGA is an open platform enabling researchers and instructors to build high-speed, hardware-accelerated networking systems. The NetFPGA is the de-facto experimental platform for line-rate implementations of network research and it continues with a new generation platform capable of 4x10Gbps. The target audience is not restricted to hardware researchers: the NetFPGA provides the ideal platform for research across a wide range of networking topics from architecture to algorithms and from energy-efficient design to routing and forwarding. The most prominent NetFPGA success is OpenFlow, which in turn has reignited the Software Defined Networking movement. NetFPGA enabled OpenFlow by providing a widely available open-source development platform capable of line-rate and was, until its commercial uptake, the reference platform for OpenFlow. NetFPGA enables high-impact network research. This seminar will combine presentation and demonstration; no knowledge of hardware programming languages (eg Verilog/VHDL) is required.
Build an Internet router and learn about clean-slate switches in a 5-day spring school will be held at Poznan University of Technology in Poznań, Poland.
This event will be like previous summer-school events but, excitingly, will be the first NetFPGA event to exclusively use the new NetFPGA 10G boards.
The NetFPGA platform originated at Stanford University and more-recently updated NetFPGA (10Gb/s) have been developed in collaboration with Cambridge University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.
By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.
Date: 20-24 of May 2013 (Monday - Friday)
Location: Poznan University of Technology, Faculty of Electronics and Telecommunications, Poznan, Poland
Street/Building: Polanka 3
We ask that attendees plan to arrive in Poznań by Sunday evening and plan to depart Saturday morning so as not to miss the gala dinner and awarding ceremony.
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The outline for this camp will be the same as other ones realized by instructors from netfpga.org groups. (http://netfpga.org/tutorials/2013_SummerCamp/)
Day 1 (Monday, May 20, 9.00 - 17.00)
Day 2 (Tuesday, May 21, 9.00 - 17.00)
Day 3 (Wednesday, May 22, 9.00 - 17.00)
Day 4 (Thursday, May 23)
Day 5 (Friday, May 24, 9.00 - 17.00)
The best project of the camp will be choosen and the prize for its developer will be granted. The sponsor of this prize is Xilinx.
Short bio of our Tutors:
ANDREW W. MOORE is a Senior Lecturer at the University of Cambridge Computer Laboratory in England, where he is part of the Systems Research Group working on issues of network and computer architecture. His research interests include enabling open-source network research and education using the NetFPGA platform, other research pursuits include low-power energy-aware networking, and novel network and systems data-center architectures. He holds B.Comp. and M.Comp. degrees from Monash University and a Ph.D. from the University of Cambridge. He is a chartered engineer with the IET and a member of the IEEE, ACM and USENIX.
GEORGINA KALOGERIDOU is a Research Assistant at the University of Cambridge Computer Laboratory, UK, where she is part of the Systems Research Group. Her research interests include open-source hardware platform (NetFPGA), digital design, hardware security and reconfigurable computing. She received the Bachelor degree in Telecommunication Systems & Networks from the Department of Telecommunication Systems & Networks, Technological Educational Institute of Messolonghi, Branch of Nafpaktos, Greece, in 2010 and the MSc Degree in Integrated Software and Hardware Systems from the Electrical & Computer Engineering Department, School of Engineering, University of Patras, Greece.
NOA ZILBERMAN is a Research Associate in the System Research Group, University of Cambridge Computer Laboratory. Her research interests include open-source network research using the NetFPGA platform, network performance, routing and switching architectures, Internet measurements and topology. She studied for her BSc, MSc and PhD in Tel Aviv University, Israel. In her last roles before joining the System Research Group, she was a researcher in the DIMES project and a chip architect in Broadcom's Network Switching group.
GIANNI ANTICHI is a Research Associate at the University of Cambridge Computer Laboratory in England, where he is part of the Systems Research Group working on issues of network and computer architecture. His research interests include open-source hardware accelerated networking systems (mainly NetFPGA), network design, network monitoring and packet classification. He received the B.E. and the M.E. degrees in telecommunications engineering and the PhD degree in information engineering from the University of Pisa, Pisa, Italy, in 2005, 2007, and 2011, respectively.
NEELAKANDAN MANIHATTY BOJAN is a Research Assistant in the Systems Research Group, University of Cambridge Computer Laboratory. His interests are open source hardware platform (NetFPGA), digital design, reconfigurable computing, energy efficiency in optical networks. He received his Bachelors in Electronics and Communication Engineering from SNS College of Technology (Coimbatore, India) in 2009. He graduated from his Erasmus Mundus Masters in Photonic Networks Engineering in 2012 from Aston University (Birmingham, UK) and Scuola Superiore Sant Anna (Pisa, Italy).
JONG H. HAN is a Research Associate in the System Research Group, University of Cambridge Computer Laboratory. His research interests are open hardware platform (NetFPGA), rapid prototype platform for network systems, and high speed and low power design for digital data communication systems. He received a PhD in Electronics Engineering from the University of Edinburgh. Before joining the System Research Group, he worked at Samsung Electronics Co where he developed wireless baseband mode SoCs.
It is possible to get to Poznan in several ways:
Registration fee covers printed materials, all lunches, and most dinners
If you have any question or problem you can mail firstname.lastname@example.org.